Production method for a semiconductor component

ABSTRACT

The invention relates to a production method for a semiconductor component, with a substrate ( 1 ) and an electrode stack ( 7, 9′, 11′, 13 ), comprising a polysilicon electrode layer ( 7 ) and a tungsten-containing electrode layer ( 9′ ) arranged thereon. Said method comprises the steps: preparation of the substrate ( 1 ); deposition of a sequence of layers, comprising the polysilicon layer ( 7 ), a tungsten-containing pre-cursor layer ( 9 ) thereon and a protective layer on the above: tempering the sequence of layers at a first temperature (T 1 ), at which a crystalline conversion occurs in the tungsten-containing pre=cursor layer ( 9 ) such that the electrode layer ( 9′ ) is formed therefrom; structuring the sequence of layers to give the electrode stack ( 7, 9′, 11′, 13 ); and formation of sidewall spacers ( 13 ) by oxidising the polysilicon layer ( 7 ) at a second temperature (T 2 ), whereby the second temperature (T 2 ) is selected to be lower than the first temperature (T 1 ) such that no crystalline conversion occurs in the electrode ( 9′ ).

[0001] The present invention relates to a method for fabricating asemiconductor component having a substrate and an electrode stack whichis arranged on the substrate and includes a polysilicon electrode layerand a tungsten-containing electrode layer above it.

[0002] The term substrate is to be understood in the general sense andmay therefore comprise both single-layer and multilayer substrates ofany desired type.

[0003] Although it can be applied to any desired semiconductorcomponents, the present invention as well as the problem on which it isbased are explained with reference to gate electrode stacks of dynamicrandom access memories (DRAMs) using silicon technology.

[0004] What are known as single-transistor cells are used in dynamicrandom access memories (DRAMs). These cells comprise a storage capacitorand a select transistor (MOSFET), which connects the storage electrodeto the bit line. The storage capacitor may be designed as a trenchcapacitor or as a stacked capacitor.

[0005] To drive the select transistor, a metalically conductive gateelectrode stack is placed onto the gate oxide. Typical gate electrodestacks are stacks comprising doped polysilicon and, above it, a tungstensilicide (WSi_(x)) or a tungsten nitride/tungsten sandwich.

[0006] Patterning of a gate electrode stack of this type, for example bya plasma etch, by means of an additional silicon nitride capping layeron the upper tungsten-containing electrode layer, together withcorresponding gate contacts, provides the metallic connection lines.

[0007] The patterned gate electrode stacks are usually subjected to athermal aftertreatment in such a manner that simultaneously theuncovered side walls are partially oxidized and the resistance in themetal is minimized by targeted phase transformation or grain growth. Thethin film of oxide which is thereby formed on the side walls of thepolysilicon improves the leakage current characteristics of thetransistors and acts as a spacer for the subsequent LDD (lightly dopeddrain) implantation. The latter sets the transistor parameters over thedefined gate length. The metallic phase transformation at typicaltemperatures of 1000 to 1080° C. leads to a reduction in the resistanceand is associated with strong grain growth in the gate metal.

[0008] In the process as currently used, the conditioning takes place atbetween 1000 and 1080° C. after the patterning of the gate electrodestack immediately before the LDD implantation. This known process leadsto the following problems.

[0009] When tungsten silicide (WSi_(x)) is used, grains grow outlaterally beyond the side faces of the gate electrode stack, which havebeen etched smooth, forming a partial alloy with the polysilicon below.These lateral projections, in particular in future technologygenerations with a feature size of <170 nm, may lead to short circuitswith adjacent metal contacts, since they may be etched open during thecontact etch.

[0010] DRAM technologies with transistor gate lengths of less than 110nm require modified cell architectures with lower resistances andconnections which are free of short circuits.

[0011] The use of tungsten without Si alloy with a tungsten nitridediffusion barrier with respect to the polysilicon below fulfils therequirements relating to the resistance. However, tungsten as gate metalis not suitable for current processes, since during the subsequentprocessing involved in thermal and oxidation processes, it escapes as agas or sublimes as WO_(x) and is precipitated at the chamber innerwalls, making it impossible to control the side wall oxidation.

[0012] The object of the present invention is to provide an improvedmethod for fabricating a semiconductor component of the type describedin the introduction which is able to prevent WSi_(x) grains from growingout and to prevent WO_(x) from being sublimed.

[0013] According to the invention, this object is achieved by thefabrication method described in claim 1.

[0014] The general idea on which the present invention is based consistsin separating the thermal aftertreatment of the gate electrode stack(phase transformation or grain growth in order to reduce the resistance)from the aftertreatment of the polysilicon (side wall oxidation), in twoindependent process steps.

[0015] All the known deposition and etching processes can be retained inthe same form. All the subsequent thermal processes can take place atlower temperatures than has hitherto been the case, since theconditioning of the gate metal has been concluded, and this has abeneficial effect on the heat budget.

[0016] Particular advantages of conditioning with a combination oftungsten nitride/tungsten result from a lower stack height beingrequired to achieve the same resistance. This results in a lessdemanding aspect ratio during application of the insulation layer andsimplifies subsequent etching processes.

[0017] Advantageous refinements and improvements of the subject matterof the invention are given in the subclaims.

[0018] According to a preferred refinement, grain growth and/or phasetransformation associated with a reduction in the resistance takes placein the precursor layer at the first temperature.

[0019] According to a further preferred refinement, thetungsten-containing precursor layer consists of tungsten silicide, thefirst temperature lying in the range from 900 to 1080° C.

[0020] According to a further preferred refinement, thetungsten-containing precursor layer consists of tungsten metal, with thefirst temperature lying in the range from 900 to 1080° C.

[0021] According to a further preferred refinement, a diffusion barrierlayer made from tungsten nitride is provided beneath thetungsten-containing precursor layer made from tungsten metal during thedeposition of the layer sequence.

[0022] According to a further preferred refinement, the protective layeris formed into a hard mark by means of a lithographic process, and thelayer sequence is patterned by means of an etching process using thishard mask.

[0023] According to a further preferred refinement, the secondtemperature lies in the range from 800 to 850° C.

[0024] According to a further preferred refinement, the electrode stackis a gate electrode stack which is located on a gate oxide layer of thesubstrate.

[0025] An exemplary embodiment of the invention is illustrated in thedrawings and is explained in more detail in the description whichfollows.

[0026]FIGS. 1a-e show the steps of an exemplary embodiment of thefabrication method according to the invention which are essential togaining an understanding of the invention; and

[0027]FIG. 2 shows a further exemplary embodiment of the fabricationmethod according to the invention.

[0028] In FIGS. 1a-e, identical reference symbols denote identical orfunctionally equivalent elements.

[0029] In accordance with FIG. 1a, first of all a substrate 1 isprovided, this substrate having active regions (not shown), such as forexample source regions and drain regions. First of all, a gate oxidelayer 5 is formed on the substrate 1 by means of a standard thermaloxidation process. A doped polysilicon layer 7 is deposited on the gateoxide layer 5, for example by means of the CVD (chemical vapordeposition) process. A tungsten silicide layer 9 is deposited on thepolysilicon layer 7 by means of a CVD process.

[0030] In a further exemplary embodiment as shown in FIG. 2, a tungstennitride layer 9 a is deposited, followed by the deposition of a tungstenlayer 9 b in the same process chamber.

[0031] Finally, a silicon nitride layer 11 is deposited, likewise bymeans of a CVD process. From here on, the process steps are once againidentical for both exemplary embodiments.

[0032] In the following process step, which is illustrated in FIG. 1b, afirst conditioning step takes place at a first temperature T1 in therange from 900 to 1080° C., preferably 1000° C. This first conditioningstep brings about phase transformation associated with a grain growthand a reduction in the resistance of the tungsten silicide layer 9,transforming this precursor layer into the final electrode layer 9′.

[0033] In other words, the first conditioning step (900 to 1080° C.) iscarried out for phase transformation, grain growth or resistancereduction after all the layers polysilicon, gate metal, silicon nitridehave been completely deposited, i.e. with a capping layer above the gatemetal, and prior to patterning of the gate electrode stacks. Thesublimation of tungsten oxide (WO_(x)) can be prevented by the cappinglayer. Furthermore, the formation of surface roughness (cavities causedby grain growth), which is inevitable during the phase transformation,and the nitride layer above is prevented. Therefore, in particular thereis no silicon nitride in the cavities, which during a subsequent gatestack etch would have a masking action in the cavities and wouldtherefore lead to short circuits.

[0034] In the next method step, the silicon nitride layer 11 ispatterned to form a hard mask 11′ by means of a standardphotolithography step, leading to the state shown in FIG. 1c.

[0035] This hard mark 11′ is then used to form the gate electrode stackfrom the layer sequence comprising the layers 5, 7, 9′ by means of astandard plasma-RIE step. This is illustrated in FIG. 1d. Then, theremaining polysilicon layer 7 is oxidized, in order to form side walloxide spacers 13, in an oxidation furnace or by means of a rapid thermaloxidation process. This leads to the state shown in FIG. 1e.

[0036] The second temperature step takes places at significantly lowertemperatures of 800 to 850° C. after the gate stack has been patterned,for the purpose of targeted side wall oxidation of the polysiliconsurfaces. Therefore, in the case of tungsten silicide (WSi_(x)), thelateral growth of the metal grains does not occur and the geometry ofthe pattern is retained, since after the gate stack etch the process ofgrain size growth or phase transformation in the gate metal hasconcluded.

[0037] The subsequent process steps are well known from the prior artand require no further explanation at this point. In particular, theabovementioned LDD implantation is carried out in a subsequent processstep.

[0038] Although the present invention has been described above on thebasis of a preferred exemplary embodiment, it is not restricted to thisembodiment, but rather can be modified in numerous ways.

[0039] In particular, the invention can be applied to any desiredcomponents and is not limited to gate electrode stacks.

[0040] List of Reference Symbols

[0041]1 Substrate

[0042]5 Gate oxide layer

[0043]7 Polysilicon layer

[0044]9, 9′ Tungsten silicide layer

[0045]11 Silicon nitride layer

[0046]13 Side wall silicon dioxide spacer

[0047]9 a Tungsten nitride layer

[0048]9 b Tungsten metal layer

1. A method for fabricating a semiconductor component having a substrate(1) and an electrode stack (7, 9′, 11′, 13) which is arranged on thesubstrate (1) and includes a polysilicon electrode layer (7) and atungsten-containing electrode layer (9′) above it, comprising the stepsof: providing the substrate (1); depositing a layer sequence comprisingthe polysilicon layer (7), a tungsten-containing precursor layer (9)above it and a protective layer (11) above that; conditioning the layersequence at a first temperature (T1) at which a crystallinetransformation takes place in the tungsten-containing precursor layer(9), so that the electrode layer (9′) is formed therefrom; patterningthe layer sequence to form the electrode stack (7, 9′, 11′, 13); andforming side wall spacers (13) by oxidizing the polysilicon layer (7) ata second temperature (T2), the second temperature (T2) being selected tobe lower than the first temperature (T1) such that no crystallinetransformation takes place in the electrode layer (9′).
 2. The method asclaimed in claim 1, characterized in that a grain growth and/or phasetransformation associated with a reduction in resistance takes place inthe precursor layer (9) at the first temperature (T1).
 3. The method asclaimed in claim 1 or 2, characterized in that the tungsten-containingprecursor layer (9) consists of tungsten silicide, and the firsttemperature (Ti) is in the range from 900 to 1080° C.
 4. The method asclaimed in claim 1 or 2, characterized in that the tungsten-containingprecursor layer (9) consists of tungsten metal (9 b), and the firsttemperature (T1) is in the range from 900 to 1080° C.
 5. The method asclaimed in claim 4, characterized in that a diffusion barrier layer madefrom tungsten nitride (9 a) is provided beneath the tungsten-containingprecursor layer (9) made from tungsten metal during the deposition ofthe layer sequence.
 6. The method as claimed in one of the precedingclaims, characterized in that the protective layer (11) is formed into ahard mask (11′) by means of a lithography process, and the layersequence is patterned by means of an etching process using this hardmask.
 7. The method as claimed in one of the preceding claims,characterized in that the second temperature (T2) is in the range from800 to 850° C.
 8. The method as claimed in one of the preceding claims,characterized in that the electrode stack (7, 9′, 11′, 13) is a gateelectrode stack which rests on a gate oxide layer (5) of the substrate.